i mean suppose L1 designated to core 1 and l2 designated to core2 l3 will be designated to all the cores.
What about the processors having 4/6 cores?
As you say L1 for core 1,L2 for core 2...so what about coes 3,4,5,6?
I don't think thats how it works.
L1 cache has the fastest access time(like you've mentioned later in your post) but stores the least amount as compared to other caches(L2,L3).Each core has their own L1 cache.